The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm
نویسندگان
چکیده
This chapter examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme that avoids memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT implementation are presented. The pipeline consists of log2N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result, the architecture speed up is M*log2N. The pipeline algorithm is configurable to any M > 1.
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